Phase-locked loops (PLLs) generate signals relative to a reference signal. A PLL adjusts a frequency of a PLL output signal based on differences in phase and/or frequency of the reference signal and the output signal. The frequency of the output signal is increased or decreased based on the difference. The phase-locked loop is, therefore, a control system using negative feedback. PLLs are used in a multitude of electronic devices such as SRAM, data communication channels, and System-on-Chips (SOCs).
PLL lock time is generally long. Analog PLLs use large filter capacitors and small charge pump currents which contribute to long lock times. In order to decrease lock time, designers have pre-charged the main low pass filter capacitor, increased the charge pump current, enabled an additional charge pump circuit, and increased the PLL bandwidth (BW). Such methods are often unsuitable because of associated increase in cost and/or degradation in performance.